Generally, one goal in the process of designing very large scale integration (VLSI) circuitry is the conversion of schematic circuit representations into artwork which incorporates detailed features of the ultimate circuit architecture. Artwork resulting from such a conversion is then generally used to generate masks used to etch a circuit on a chip.
Two approaches for generating the desired artwork are known in the art. A first prior art approach is to generate the desired artwork by hand. However, manual artwork generation is slow, prone to error, and extremely time consuming. Moreover, minor changes in sections of such artwork may require rework of entire circuit designs.
A second prior art approach involves the use of an automated tool to synthesize the artwork from a schematic or functional representation of the desired circuit. However, prior art automated tools generally control a great deal of the layout of resulting artwork, thereby depriving a human circuit designer of any significant control over a circuit's final layout. This lack of control over a circuit's layout may make subsequent circuit debugging difficult. Moreover, where an automated tool controls the circuit layout, the efficiency of the layout will generally be completely determined by decisions made by the automated tool. If the automated tool has not been updated to reflect the latest advances in VLSI processes, the resulting circuit may not perform appropriately, if at all.